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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. tps55340-q1 slvsbv5a ? june 2014 ? revised july 2016 tps55340-q1 integrated 5-a, wide input range boost, sepic, or flyback dc-dc converter 1 (1) for limitations, see the switching frequency section. 1 features 1 ? qualified for automotive applications ? aec-q100 qualified with the following results: ? device temperature grade 1: ? 40 c to 125 c ? device hbm esd classification level 2 ? device cdm esd classification level c6 ? internal 5-a, 40-v low-side mosfet switch ? 2.9 to 38-v input voltage range ? 0.7% reference voltage ? 0.5-ma operating quiescent current ? 2.7- a shutdown supply current ? fixed-frequency current mode pwm control ? frequency adjustable from 100 khz to 2.5 mhz (1) ? synchronization capability to external clock ? adjustable soft-start time ? pulse-skipping for higher efficiency at light loads ? cycle-by-cycle current-limit, thermal shutdown, and uvlo protection ? wqfn-16 (3 mm 3 mm) package with powerpad ? ? wide ? 40 c to 150 c operating t j range 2 applications ? boost, sepic, and flyback topologies ? automotive pre-boost applications to support start-stop requirements ? usb power delivery ? industrial power systems 3 description the tps55340-q1 device is a monolithic non- synchronous switching converter with integrated 5-a, 40-v power switch. the device can be configured in several standard switching-regulator topologies, including boost, sepic and isolated flyback. the device has a wide input voltage range to support applications with input voltage from 2.9 to 38-v. the tps55340-q1 device regulates the output voltage with current mode pwm (pulse width modulation) control, and has an internal oscillator. the switching frequency of pwm is set by either an external resistor or by synchronizing to an external clock signal. the user can program the switching frequency from 100 khz to 2.5 mhz. the device features a programmable soft-start function to limit inrush current during start-up and has other built-in protection features including cycle-by- cycle over current-limit and thermal shutdown. the tps55340-q1 device is available in a small 3- mm 3-mm 16-pin wqfn package with powerpad for enhanced thermal performance. device information (1) part number package body size (nom) tps55340-q1 wqfn (16) 3.00 mm 3.00 mm (1) for all available packages, see the orderable addendum at the end of the datasheet. typical application for boost efficiency vs output current 50 55 60 65 70 75 80 85 90 95 100 0.0 0.4 0.8 1.2 1.6 2.0 2.4 efficiency (%) vi = 5 v vi = 12 v vi = 15 v c021 v o = 24 v ? s = 600 khz v i = 5 v v i = 12 v v i = 15 v output current (a) tps55340-q1 vinen swsw sw freqss comp sync fb pgndpgnd pgnd v i v o r (sl) r (sh) l d c i c o r (freq) c ss r (c) c (c) agnd productfolder sample &buy technical documents tools & software support &community
2 tps55340-q1 slvsbv5a ? june 2014 ? revised july 2016 www.ti.com product folder links: tps55340-q1 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 4 6.1 absolute maximum ratings ..................................... 4 6.2 esd ratings .............................................................. 4 6.3 recommended operating conditions ....................... 4 6.4 thermal information .................................................. 4 6.5 electrical characteristics ........................................... 5 6.6 typical characteristics .............................................. 6 7 detailed description .............................................. 9 7.1 overview ................................................................... 9 7.2 functional block diagram ......................................... 9 7.3 feature description ................................................... 9 7.4 device functional modes ........................................ 12 8 application and implementation ........................ 14 8.1 application information ............................................ 14 8.2 typical applications ................................................ 14 9 power supply recommendations ...................... 28 10 layout ................................................................... 28 10.1 layout guidelines ................................................. 28 10.2 layout example .................................................... 28 11 device and documentation support ................. 29 11.1 receiving notification of documentation updates 29 11.2 community resources .......................................... 29 11.3 trademarks ........................................................... 29 11.4 electrostatic discharge caution ............................ 29 11.5 glossary ................................................................ 29 12 mechanical, packaging, and orderable information ........................................................... 29 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from original (june 2014) to revision a page ? changed title from dc-dc regulator to dc-dc converter ................................................................................................... 1 ? changed the applications section .......................................................................................................................................... 1 ? changed the handling ratings table to esd ratings and moved the storage temperature to the absolute maximum ratings table ........................................................................................................................................................................... 4 ? changed the switching frequency section to add recommendation for using an external synchronous clock when setting the switching frequency higher than 1.2 mhz ........................................................................................................... 10 ? changed the equation to calculate r3 in the compensating the control loop (r3, c4, and c5) section .......................... 21 ? added the receiving notification of documentation updates and community resources sections .................................. 29
3 tps55340-q1 www.ti.com slvsbv5a ? june 2014 ? revised july 2016 product folder links: tps55340-q1 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 5 pin configuration and functions 16-pin qfn with powerpad rte package top view pin functions pin description name no. agnd 6 signal ground of the ic comp 7 output of the transconductance error amplifier. an external rc network connected to this pin compensates the regulator feedback loop. en 3 enable pin. when the voltage of this pin falls below the enable threshold for more than 1 ms, the ic turns off. fb 8 error amplifier input and feedback pin for positive voltage regulation. connect the fb pin to the center tap of a resistor divider to program the output voltage. freq 9 switching frequency program pin. an external resistor connected between the freq pin and the agnd pin sets the switching frequency. nc 10 this pin is reserved and must be connected to ground. 14 pgnd 11 power ground of the ic. the pgnd pin is connected to the source of the internal power mosfet switch. 12 13 ss 4 soft-start programming pin. a capacitor between the ss pin and agnd pin programs soft-start timing. sw 1 sw is the drain of the internal power mosfet. connect the sw pin to the switched side of the boost or sepic inductor or the flyback transformer. 15 16 sync 5 switching-frequency synchronization pin. an external clock signal can set the switching frequency between 200 khz and 1 mhz. if this pin is not used, it must be tied to agnd. vin 2 the input supply pin to the ic. connect the vin pin to a supply voltage between 2.9 v and 32 v. the voltage on the vin pin can be different from the boost power-stage input. powerpad the powerpad must be soldered to the agnd. if possible, use thermal vias to connect the powerpad to pcb ground-plane layers for improved power dissipation. powerpad 16 ss en vin sw freq nc pgnd pgnd sw sw nc pgnd sync agnd comp fb 15 14 13 5 6 7 8 1 23 4 12 11 10 9
4 tps55340-q1 slvsbv5a ? june 2014 ? revised july 2016 www.ti.com product folder links: tps55340-q1 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to network ground pin. 6 specifications 6.1 absolute maximum ratings over operating temperature range (unless otherwise noted) (1) min max unit input voltage vin (2) ? 0.3 40 v en (2) ? 0.3 40 v fb, freq, and comp (2) ? 0.3 3 v ss (2) ? 0.3 5 v sync (2) ? 0.3 7 v output voltage sw (2) ? 0.3 40 v sw ( < 10 ns transient) (2) ? 5 40 v operating junction temperature ? 40 150 c storage temperature, t stg ? 65 150 c (1) aec q100-002 indicates that hbm stressing shall be in accordance with the ansi/esda/jedec js-001 specification. 6.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per aec q100-002 (1) 2000 v charged-device model (cdm), per aec q100-011 1000 6.3 recommended operating conditions min nom max unit v i input voltage 2.9 38 v v o output voltage v i 38 v v (en) en voltage 0 38 v v syn external switching-frequency logic input 0 5 v t a operating free-air temperature ? 40 125 c t j operating junction temperature ? 40 150 c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 6.4 thermal information thermal metric (1) tps55340-q1 unit rte (wqfn) 16 pins r ja junction-to-ambient thermal resistance 43.3 c/w r jc(top) junction-to-case (top) thermal resistance 38.7 c/w r jb junction-to-board thermal resistance 14.5 c/w jt junction-to-top characterization parameter 0.4 c/w jb junction-to-board characterization parameter 14.5 c/w r jc(bot) junction-to-case (bottom) thermal resistance 3.5 c/w
5 tps55340-q1 www.ti.com slvsbv5a ? june 2014 ? revised july 2016 product folder links: tps55340-q1 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 6.5 electrical characteristics v i = 5 v, t j = ? 40 c to 150 c, unless otherwise noted. typical values are at t a = 25 c. parameter test conditions min typ max unit supply current v i input voltage range 2.9 38 v i q operating quiescent current into vin device non-switching, v (fb) = 2 v 0.5 ma i l(sd) shutdown current en = gnd 2.7 10 a v (uvlo) under-voltage lockout threshold v i(f) 2.5 2.7 v v hys under-voltage lockout hysteresis 120 140 160 mv enable and reference control v (en)(r) en threshold voltage en rising input 0.9 1.08 1.3 v v (en)(f) en threshold voltage en falling input 0.74 0.92 1.125 v v (en)(hys) en threshold hysteresis 0.16 v r (en) en pull down resistor 400 950 1600 k ? t off shutdown delay, ss discharge en high to low 1 ms v (sync)h syn logic high voltage 1.2 v (sync)l syn logic low voltage 0.4 v voltage and current control v ref voltage feedback regulation voltage 1.204 1.229 1.254 v t a = 25 c 1.22 1.229 1.238 i ib(fb) voltage feedback input bias current t a = 25 c 1.6 20 na i (comp_sink) comp-pin sink current v (fb) = v ref + 200 mv, v (comp) = 1 v 42 a i s(comp) comp-pin source current v (fb) = v ref ? 200 mv, v (comp) = 1 v 42 a v c(comp) comp pin clamp voltage high clamp, v (fb) = 1 v 3.1 v low clamp, v (fb) = 1.5 v 0.75 v (comp_th) comp pin threshold duty cycle = 0% 1.04 v g m(ea) error amplifier transconductance 240 360 440 mho r o(ea) error amplifier output resistance 10 m ? (ea) error amplifier crossover frequency 500 khz frequency ? frequency r (freq) = 480 k 75 94 130 khz r (freq) = 80 k 460 577 740 r (freq) = 40 k 920 1140 1480 r (freq) = 18 k 2261 2549 2837 d max maximum duty cycle v (fb) = 1 v, r (freq) = 80 k 89% 96% v (freq) freq pin voltage 1.25 v t w(on) min minimum on pulse width r (freq) = 80 k 77 107 ns power switch r ds(on) n-channel mosfet on-resistance v i = 5 v 60 110 m v i = 3 v 70 120 i ln_nfet n-channel leakage current v ds = 25 v, t a = 25 c 2.1 a ocp and ss i lim n-channel mosfet current limit d = d max 5.25 6.6 7.75 a i b(ss) soft-start bias current v (ss) = 0 v 6 a thermal shutdown t sd thermal shutdown threshold 165 c t hys thermal shutdown threshold hysteresis 15 c
6 tps55340-q1 slvsbv5a ? june 2014 ? revised july 2016 www.ti.com product folder links: tps55340-q1 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 6.6 typical characteristics v i = 5 v, t a = 25 c (unless otherwise noted) figure 1. error amplifier transconductance vs temperature figure 2. switch current-limit vs temperature figure 3. feedback voltage reference vs temperature figure 4. static drain-source on-state resistance (r ds(on) ) vs temperature figure 5. frequency vs freq resistance low frequency range figure 6. frequency vs freq resistance high frequency range 0 20 40 60 80 100 120 50 25 0 25 50 75 100 125 150 resistance (m temperature (c) vi = 3 v vi = 5 v vi = 12 v c004 v i = 3 v v i = 5 v v i = 12 v 1.220 1.222 1.224 1.226 1.228 1.230 50 25 0 25 50 75 100 125 150 voltage reference (v) temperature ( )c c003 300 320 340 360 380 400 50 25 0 25 50 75 100 125 150 transconductance (a/v) temperature (c ) c001 1 2 3 4 5 6 7 8 50 25 0 25 50 75 100 125 150 current-limit threshold (a) temperature (c) c002 freq resistance (k : ) switching frequency (khz) 100 150 200 250 300 350 400 450 500 100 150 200 250 300 350 400 450 500 d003 freq resistance (k : ) switching frequency (khz) 0 20 40 60 80 100 500 700 900 1100 1300 1500 1700 1900 2100 2300 2500 d005
7 tps55340-q1 www.ti.com slvsbv5a ? june 2014 ? revised july 2016 product folder links: tps55340-q1 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated typical characteristics (continued) v i = 5 v, t a = 25 c (unless otherwise noted) t a = 25 c figure 7. minimum switching frequency for quick recovery from frequency foldback figure 8. frequency vs temperature r (freq) = 80 k figure 9. non-foldback frequency vs foldback frequency figure 10. comp clamp voltage vs temperature figure 11. input voltage uvlo vs temperature figure 12. enable voltage vs temperature 2.50 2.52 2.54 2.56 2.58 2.60 2.62 2.64 2.66 2.68 2.70 50 25 0 25 50 75 100 125 150 input voltage (v) temperature (c) uvlo start uvlo stop c009 1 1 1 1 1 1 1 50 25 0 25 50 75 100 125 150 enable voltage (v) temperature (c) en voltage rising en voltage falling c010 0 100 200 300 400 500 600 700 50 25 0 25 50 75 100 125 150 frequency (khz) temperature (c) non-foldback foldback c007 1 1 2 2 3 3 4 50 25 0 25 50 75 100 125 150 comp voltage (v) temperature (c) comp-terminal clamp high comp-terminal clamp low c008 0 200 400 600 800 1000 1200 1400 50 25 0 25 50 75 100 125 150 frequency (khz) temperature (c) rfreq = 40 k rfreq = 80 k rfreq = 480 k c006 r (freq) = 40 k r (freq) = 80 k r (freq) = 480 k voltage on the vin pin (v) frequency (khz) 0 5 10 15 20 25 30 35 40 0 50 100 150 200 250 300 350 400 d006
8 tps55340-q1 slvsbv5a ? june 2014 ? revised july 2016 www.ti.com product folder links: tps55340-q1 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated typical characteristics (continued) v i = 5 v, t a = 25 c (unless otherwise noted) r (freq) = 80 k figure 13. maximum duty cycle vs temperature r (freq) = 80 k figure 14. minimum on time vs temperature figure 15. shutdown current vs temperature figure 16. supply current vs temperature 0.3 0.6 0.9 1.2 1.5 1.8 2.1 50 25 0 25 50 75 100 125 150 supply current (ma) temperature (c) switching non-switching c014 94 95 96 97 98 99 100 50 25 0 25 50 75 100 125 150 maximum duty cycle (%) temperature (c) c011 70 75 80 85 90 95 100 50 25 0 25 50 75 100 125 150 minimum on time (ns) temperature (c) c012 1 2 3 4 5 6 7 8 50 25 0 25 50 75 100 125 150 shutdown current (a) temperature (c) c013
9 tps55340-q1 www.ti.com slvsbv5a ? june 2014 ? revised july 2016 product folder links: tps55340-q1 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7 detailed description 7.1 overview the tps55340-q1 device is a monolithic non-synchronous switching converter with an integrated 5-a, 40-v power switch. the device can be configured in several standard switching-regulator topologies, including boost, sepic, and isolated flyback. the device has a wide input voltage range to support applications with input voltage from multi-cell batteries or regulated 3.3-v, 5-v, 12-v, and 24-v power rails. 7.2 functional block diagram 7.3 feature description 7.3.1 operation if designed as a boost converter, the tps55340-q1 device regulates the output with current-mode pulse-width- modulation (pwm) control. the pwm-control circuitry turns on the switch at the beginning of each oscillator clock cycle. the input voltage is applied across the inductor and stores the energy as inductor current ramps up. during this portion of the switching cycle, the load current is provided by the output capacitor. when the inductor current reaches a threshold level set by the error amplifier output, the power switch turns off and the external schottky diode is forward biased to allow the inductor current to flow to the output. the inductor transfers stored energy to replenish the output capacitor and supply the load current. this operation repeats every switching cycle. the duty cycle of the converter is determined by the pwm-control comparator which compares the error amplifier output and the current signal. the oscillator frequency is programmed by the external resistor or synchronized to an external clock signal. sw ramp generator losslesscurrent sense en pgnd erroramp vin pwm control comp ss freq sync fb agnd 1.229-v reference s oscillator gatedriver
10 tps55340-q1 slvsbv5a ? june 2014 ? revised july 2016 www.ti.com product folder links: tps55340-q1 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated feature description (continued) a ramp signal from the oscillator is added to the inductor current ramp to provide slope compensation. slope compensation is required to avoid sub-harmonic oscillation that is intrinsic to peak-current mode control at duty cycles higher than 50%. if the inductor value is too small, the internal slope compensation may not be adequate to maintain stability. the pwm control feedback loop regulates the fb pin to a reference voltage through a transconductance error amplifier. the output of the error amplifier is connected to the comp pin. an external rc-compensation network connected to the comp pin is chosen for feedback loop stability and optimum transient response. 7.3.2 switching frequency the switching frequency is set by a resistor (r (freq) ) connected to the freq pin of the tps55340-q1 device. the relationship between the resistance of r (freq) and frequency is shown in the figure 5 . do not leave this pin open. a resistor must always be connected from the freq pin to ground for proper operation. use equation 1 to calculate the resistor value required for a desired frequency. r (freq) (k ) = 57500 ? s ? 1.03 (khz) (1) for the given resistor value, use equation 2 to calculate the corresponding frequency. ? s (khz) = 41600 r (freq) ? 0.97 (k ) (2) the tps55340-q1 switching frequency can synchronized to an external clock signal that is applied to the sync pin. the required logic levels of the external clock are shown in the electrical characteristics table. the recommended duty cycle of the clock is in the range of 10% to 90%. a resistor must be connected from the freq pin to ground when the converter is synchronized to the external clock and the external clock frequency must be within 20% of the corresponding frequency set by the resistor. for example, if the frequency programmed by the freq pin resistor is 600 khz, the external clock signal must be in the range of 480 to 720 khz. with a switching frequency below 280 khz (typical) after the tps55340-q1 enters frequency foldback as described in the overcurrent protection and frequency foldback section, if a load remains when the overcurrent condition is removed the output may not recover to the set value. for the output to return to the set value the load must be removed completely or the tps55340-q1 power cycled with the en pin or vin pin. select a nominal switching frequency of 350 khz for quicker recovery from frequency foldback. when setting the switching frequency higher than 1.2 mhz, ti recommends using an external synchronous clock as the switching frequency to ensure that the pulse-skipping function works at a light load. when using the internal switching frequency above 1.2 mhz, the tps55340-q1 device might not pulse skip as described in the minimum on time and pulse skipping section. when the pulse-skipping function does not work at light loads, the tps55340-q1 device always operates in pwm mode with a minimum on pulse width. this causes the output voltage to be higher than the set value with the resistor divider at the fb pin. this occurs in minimum duty cycle conditions such as when there is light output load or when the input voltage is close to the set output voltage in a boost topology. in the light load condition a minimum output load will keep the output voltage at the set value in a boost topology. the minimum load needed can be estimated with equation 3 or equation 4 using the maximum minimum on time of 107 ns and a parasitic c (sw) capacitance of 150 pf. for example when boosting 5 v to 12 v with 2.5 mhz switching frequency and 2- h inductor the worst case minimum output load is 36 ma. when v o ? v i < v i (3) when v o ? v i > v i (4) 2 i w(on) i sw o o i v t min v l c fs i min 2 l v v u u u u u u 2 i w(on) o i sw o o i v t min v v l c fs i min 2 l v v u u u u u u
11 tps55340-q1 www.ti.com slvsbv5a ? june 2014 ? revised july 2016 product folder links: tps55340-q1 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated feature description (continued) 7.3.3 overcurrent protection and frequency foldback the tps55340-q1 device provides cycle-by-cycle over-current protection that turns off the power switch when the inductor current reaches the overcurrent limit threshold. the pwm circuitry resets at the beginning of the next switch cycle. during an overcurrent event, the output voltage begins to droop as a function of the load on the output. when the fb voltage through the feedback resistors, drops lower than 0.9 v, the switching frequency is automatically reduced to ? of the normal value. figure 9 shows the non-foldback frequency with an 80-k ? timing resistor and the corresponding foldback frequency. the switching frequency does not return to normal until the overcurrent condition is removed and the fb voltage increases above 0.9 v. the frequency foldback feature is disabled during soft-start. 7.3.3.1 minimum on time and pulse skipping the tps55340-q1 pwm control system has a minimum pwm pulse width of 77 ns (typical). this minimum on- time determines the minimum duty cycle of the pwm, for any set switching frequency. when the voltage regulation loop of the tps55340-q1 device requires a minimum on-time pulse width less than 77 ns, the ic enters pulse-skipping mode. in this mode, the device power switches off for several switching cycles to prevent the output voltage from rising above the desired regulated voltage. this operation typically occurs in light load conditions when the pwm operates in discontinuous conduction mode. pulse skipping increases the output ripple as shown in figure 23 . 7.3.4 voltage reference and setting output voltage an internal voltage reference provides a precise 1.229-v voltage reference at the error amplifier non-inverting input. to set the output voltage, select the fb pin resistor r (sh) and r (sl) as shown in equation 5 . (5) 7.3.5 soft-start the tps55340-q1 device has a built-in soft-start circuit that significantly reduces the start-up current spike and output voltage overshoot. when the ic is enabled, an internal bias current source (6 a typical) charges a capacitor (c (ss) ) on the ss pin. the voltage at the capacitor clamps the output of the internal error amplifier that determines the peak current and duty cycle of the pwm controller. limiting the peak switch current during start- up with a slow ramp on the ss pin reduces in-rush current and output voltage overshoot. when the capacitor reaches 1.8 v, the soft-start cycle is complete and the soft-start voltage no longer clamps the error amplifier output. when the en is pulled low for at least 1 ms, the ic enters the shutdown mode and the ss capacitor is discharged through a 5-k ? resistor to prepare for the next soft-start sequence. 7.3.6 slope compensation to prevent sub-harmonic oscillations, the tps55340-q1 device uses internal slope compensation. use equation 6 to calculate the sensed current slope of boost converter. (6) use equation 7 to calculate the slope compensation dv/dt. (7) in a converter with current mode control, in addition to the output voltage feedback loop, the inner current loop including the inductor current sampling effect as well as the slope compensation on the small-signal response must be taken into account as calculated in equation 8 . ( ) ( ) 0.32 v r freq 0.5 a s e 16 (1 d) 6 pf 6 pf ? ? ? ? ? ? = + - ( ) ( ) v i s r n sense l = ( ) ( ) sh o sl r v 1.229 v 1 r ? ? ? = + ? ?
12 tps55340-q1 slvsbv5a ? june 2014 ? revised july 2016 www.ti.com product folder links: tps55340-q1 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated feature description (continued) where ? r (sense) (15 m ) is the equivalent current-sense resistor ? r (freq) is the timing resistor used to set frequency ? d is the duty cycle (8) note if s (n) < < s (e) , the converter operates in voltage mode control rather than operating current mode control, and equation 8 is no longer valid. 7.3.7 enable and thermal shutdown the tps55340-q1 device enters shutdown when the en voltage is less than 0.68 v (minimum) for more than 1ms. in shutdown, the input supply current for the device is less than 10 a (maximum). the en pin has an internal 950-k pulldown resistor to disable the device if the pin is floating. an internal thermal shutdown turns off the device when the junction temperature exceeds 165 c (typical). the device restarts when the junction temperature drops by 15 c. 7.3.8 undervoltage lockout (uvlo) an undervoltage-lockout circuit prevents misoperation of the device at input voltages below 2.5 v (typical). when the input voltage is below the uvlo threshold, the device remains off and the internal power mosfet turns off. the uvlo threshold is set below the minimum operating voltage of 2.9 v to ensure that a transient vin dip does not cause the device to reset. for the input voltages between uvlo threshold and 2.9 v, the device attempts to operate, but the electrical specifications are not ensured. 7.3.9 thermal considerations the maximum ic junction temperature must be restricted to 150 c under normal operating conditions. this restriction limits the power dissipation of the tps55340-q1 device. the tps55340-q1 device features a thermally enhanced qfn package. this package includes a powerpad that improves the thermal capabilities of the package. the thermal resistance of the qfn package in any application greatly depends on the pcb layout and the powerpad connection. the powerpad must be soldered to the analog ground on the pcb. use thermal vias underneath the powerpad to achieve good thermal performance. 7.4 device functional modes 7.4.1 operation with v i < 2.9 v (minimum v i ) the tps55340-q1 device operates with input voltages above 2.9 v. the typical uvlo voltage (turning off) is 2.5 v and the tps55340-q1 device remains off at input voltages lower than that point. for the input voltages between uvlo threshold and 2.9 v, the device attempts to operate, but the electrical specifications are not ensured. 7.4.2 operation with en control the enable rising-edge threshold voltage is 1.08 v (typical) with 0.16 v hysteresis (typical). with the en pin held below the turn-off voltage the device is disabled and switching is inhibited. the ic quiescent current is reduced in this state. when the input voltage is above the uvlo threshold and the en pin voltage increases above the rising edge threshold, the device becomes active. switching enables and the soft-start sequence initiates. the tps55340-q1 device starts at the soft-start time determined by the external soft-start capacitor. ( ) ( ) ( ) e n 1 he (s) s s 1 (1 d) 0.5 s 2 s 1 2 ? s ? s = ? ? ? + - - ? ? ? ? + + p
13 tps55340-q1 www.ti.com slvsbv5a ? june 2014 ? revised july 2016 product folder links: tps55340-q1 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated device functional modes (continued) 7.4.3 operation at light loads the device is designed to operate in high-efficiency pulse-skipping mode under light load conditions. discontinuous-conduction-mode (dcm) operation initiates when the switch current falls to 0 a. during dcm operation, the catch diode stops conducting when the switch current falls to 0 a. the switching node (the sw pin) waveform takes on the characteristics of discontinuous-conduction-mode (dcm) operation as shown in figure 22 . as the load decreases further and when the voltage-regulation loop of tps55340-q1 device requires an on-time pulse width less than the minimum pwm pulse width of 77 ns (typical), the ic enters pulse-skipping mode. in this mode, the device holds the power switch off for several switching cycles to prevent the output voltage from rising too much above the desired regulated voltage.
14 tps55340-q1 slvsbv5a ? june 2014 ? revised july 2016 www.ti.com product folder links: tps55340-q1 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 8 application and implementation 8.1 application information the tps55340-q1 device can be configured in several standard switching-regulator topologies, including boost, sepic, and isolated flyback. for example, the device configured in boost topology is widely used to convert a lower dc voltage to a higher dc voltage with a maximum available switching current of 5.25 a. use the following design procedure to select component values for a boost converter design or sepic design for the tps55340- q1 device. alternately, use the webench ? software to generate a complete design. the webench software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. this section presents a simplified discussion of the design process. 8.2 typical applications the following section provides a step-by-step design approach for configuring the tps55340-q1 device as a voltage regulating boost converter, as shown in figure 17 . when configured as sepic or flyback converter, a different design approach is required. a design example of sepic converter is provided in the tps55340-q1 sepic converter section. 8.2.1 tps55340-q1 boost converter figure 17. boost converter application schematic 1 1 off 1 en on gnd not populated vout sync gnd gnd vin vin gnd gnd vout 24v, 1.9a sw comp loop 5v - 12v jp1 j1 l110uh tp1 c4 0.1uf tp4 tp3 r4 78.7k tp2 j7 j5 j3 j6 r32.55k c5 100pf j4 j2 c3 0.047uf c7 0.1uf r210.0k r550 c1 r60 c84.7uf r1187k 1 sw 2 vin 3 en 4 ss 5 sync 6 agnd 7 comp 8 fb 9 freq 10 nc 11 pgnd 12 pgnd 13 pgnd 14 nc 15 sw 16 sw 17 pwpd u1 tps55340-q1 c94.7uf c104.7uf c6 c210uf d1 tp5 vin vin sync sync
15 tps55340-q1 www.ti.com slvsbv5a ? june 2014 ? revised july 2016 product folder links: tps55340-q1 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated typical applications (continued) 8.2.1.1 design requirements for this design example, use the parameters listed in table 1 . these parameters are typically determined at the system level. table 1. key parameters of boost converter example design parameter example value output voltage 24 v input voltage 5 v to 12 v maximum output current 800 ma transient response 50% load step ( v o = 3%) 960 mv output voltage ripple (0.5% of v o ) 120 mv 8.2.1.2 detailed design procedure 8.2.1.2.1 selecting the switching frequency (r4) the first step of this design procedure is to determine the switching frequency of the regulator. consider the tradeoffs of a higher switching frequency versus a lower switching frequency. a higher switching frequency allows for the use of a lower-valued inductor and smaller output capacitors which leads to the smallest solution size. a lower switching frequency results in a larger solution size but better efficiency. in general, the selected switching frequency allows for the minimum tolerable efficiency to avoid excessively large external components. a switching frequency of 600 khz is a good trade-off between efficiency and solution size. the appropriate resistor value is selected based on the resistance versus frequency graph (see figure 5 ) or calculated using equation 1 . the value of r4 is calculated to be 78.4 k and the nearest standard value resistor of 78.7 k is selected. a resistor must be placed from the freq pin to ground, even if an external oscillation is applied for synchronization. 8.2.1.2.2 determining the duty cycle the input-to-output voltage-conversion ratio of the tps55340-q1 device is limited by the worst-case maximum duty cycle of 89% and the minimum duty cycle which is determined by the minimum on-time of 77 ns and the switching frequency. use equation 9 to calculate the minimum duty cycle. selecting a 600-khz switching frequency, the minimum duty cycle is calculated as 4%. d (ps) = t on min ? s (9) the duty cycle at which the converter operates is dependent on the mode in which the converter is running. if the converter is running in discontinuous conduction mode (dcm), where the inductor current ramps to zero at the end of each cycle, the duty cycle varies with changes of the load much more than when running in continuous conduction mode (ccm). in continuous conduction mode, where the inductor maintains a minimum dc current, the duty cycle is related primarily to the input and output voltages as calculated with equation 10 . assume a 0.5- v drop (v (d) ) across the schottky rectifier. at the minimum input of 5 v, the duty cycle is 80%. at the maximum input of 12 v, the duty cycle is 51%. (10) at light loads the converter operates in dcm. in this case the duty cycle is a function of the load, input voltage, output voltages, inductance, and switching frequency as calculated in equation 11 . the light-load duty cycle can be calculated only after an inductance is selected (see the selecting the inductor (l1) section). while operating in dcm with very-light load conditions the duty cycle demand forces the tps55340-q1 device to operate with the minimum on time. the converter then begins pulse skipping which can increase the output ripple. (11) ( ) o i o s d i 2 (v v v ) l i ? d v + - = ( ) ( ) o i d o v v v d v v d + - = +
16 tps55340-q1 slvsbv5a ? june 2014 ? revised july 2016 www.ti.com product folder links: tps55340-q1 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated all converters using a diode as the freewheeling or catch component have a load-current level at which the converters transition from dcm to ccm. the transit from dcm to ccm is the point when the inductor current falls to zero during the off-time of the power switch. at higher load currents, the inductor current does not fall to zero and the diode and switch current assume a trapezoidal wave-shape as opposed to a triangular wave-shape. the load current boundary between discontinuous conduction and continuous conduction is calculated for a set of converter parameters as shown in equation 12 . where ? v o is the output voltage of the converter in volts (v) ? v (d) is the forward conduction voltage drop across the rectifier or catch diode in volts (v) ? v i is the input voltage to the converter in volts (v) ? i o is the output current of the converter in amperes (a) ? l is the inductor value in henries (h) ? ? s is the switching frequency in hertz (hz) (12) for loads higher than the result of the equation 12 , the duty cycle is given by equation 10 . for loads less than the results of equation 12 , the duty cycle is given equation 11 . unless otherwise stated, the design equations that follow assume that the converter is running in continuous conduction mode, which typically results in a higher efficiency for the power levels of this converter. 8.2.1.2.3 selecting the inductor (l1) the selection of the inductor affects steady state operation as well as transient behavior and loop stability. because of these factors, the inductor is the most important component in the power-regulator design. there are three important inductor specifications: inductor value, dc resistance, and saturation current. considering inductor value alone is not enough. inductor values can have 20% tolerance with no current bias. when the inductor current approaches saturation level, the effective inductance can fall to a fraction of the zero current value. the minimum value of the inductor must meet the inductor current ripple ( i l ) requirement at worst case. in a boost converter, the maximum inductor-current ripple occurs at 50% duty cycle. for applications where duty cycle is always smaller or larger than 50%, use equation 14 to calculate the minimum inductance with the duty cycle as close to 50% as possible and corresponding input voltage. for applications that must operate with 50% duty cycle when input voltage is somewhere between the minimum and the maximum input voltage, use equation 15 . k (ind) is a coefficient that represents the amount of inductor ripple current relative to the maximum input current (i (m_dc) = i l avg). use equation 13 to calculate the maximum input current, with an estimated efficiency based on similar applications ( (est) ). the inductor ripple current is filtered by the output capacitor. therefore, choosing high inductor ripple currents impacts the selection of the output capacitor because the output capacitor must have a ripple-current rating equal-to or greater-than the inductor ripple current. in general, the inductor ripple value (k (ind) ) is at the discretion of the designer. however, the following guidelines can be used for selecting the value for k (ind) . for ccm operation, ti recommends to use k (ind) values in the range of 0.2 to 0.4. selecting a value for k (ind) that is closer to 0.2 results in a larger inductance value, maximizes the potential output current of the converter, and minimizes electromagnetic interference (emi). selecting a value for k (ind) that is closer to 0.4 results in a smaller inductance value, a physically smaller inductor, and improved transient response. however, a k (ind) value close to 0.4 can result in potentially worse emi and lower efficiency. using an inductor with a smaller inductance value can result in the converter operating in dcm. operating in dcm reduces the maximum output current of the boost converter, causes larger input voltage and output voltage ripple, and reduces efficiency. for this design, a value of 0.3 for k (ind) was selected along with a conservative efficiency estimate of 85% with the minimum input voltage and maximum output current. use equation 14 to calculate the minimum output inductance with the maximum input voltage because this equation corresponds to duty cycle closest to 50%. the maximum input current is estimated at 4.52 a and the minimum inductance is 7.53 h. a standard value of 10 h is selected. ( ) ( ) ( ) ( ) o i i d o(cr ) o s d 2 2 v v v v i 2 v v ? l + - = +
17 tps55340-q1 www.ti.com slvsbv5a ? june 2014 ? revised july 2016 product folder links: tps55340-q1 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated (13) (14) (15) after selecting the inductance, the required current ratings can be calculated. use equation 16 to calculate the ripple using the selected inductance. at a minimum input voltage, the inductor has the largest current ripple, therefore v i min is used in equation 16 . use equation 17 and equation 18 to calculate the root mean square (rms) and peak inductor current. for this design the current ripple is 663 ma, the rms inductor current is 4.52 a, and the peak inductor current is 4.85 a. ti recommends that the peak inductor current rating of the selected inductor be 20% higher to account for transients during power up, faults, or transient load conditions. the most conservative approach is to specify an inductor with a saturation current greater than the maximum peak current- limit of the tps55340-q1 device. this approach helps to avoid saturation of the inductor. the selected inductor for this design was a w rth elektronik 74437368100. this inductor has a saturation current rating of 12.5 a, rms current rating of 5.2 a, and typical dcr of 27 m . (16) (17) (18) the tps55340-q1 device has built-in slope compensation to avoid subharmonic oscillation associated with current mode control. if the inductor value is too small, the slope compensation may not be adequate, and the loop can be unstable. 8.2.1.2.4 computing the maximum output current the overcurrent limit for the integrated power mosfet limits the maximum input current and thus the maximum input power for a given input voltage. maximum output power is less than maximum input power because of power conversion losses. therefore, the current-limit setting, input voltage, output voltage, and efficiency can all change the maximum current output (i o max). the current-limit clamps the peak inductor current and therefore the ripple must be subtracted to derive maximum dc current. decreasing the k (ind) value or designing for a higher efficiency increases the maximum output current. use the selected inductance or the selected k (ind) value to calculate the maximum output current. use equation 19 , the minimum input voltage, and minimum peak current-limit (i (lim) ) of 5.25 a to calculate the maximum output current. (19) for this design, with a 5-v input boosted to 24-v output, a 10- h inductor with an assumed the schottky forward voltage of 0.5 v, and estimated efficiency of 85%, the maximum output current is calculated to be 871 ma. with a 12-v input and increased estimated efficiency of 90%, the maximum output current calculated value increases to 2.13 a. this circuit was evaluated to the maximum output currents with both the minimum and maximum input voltage. ( ) ( ) ( ) ( ) ( ) ind l i lim est i lim est o o o k i v min i 1 v min i 2 2 i max v v ? ? d ? ? ? - h - h ? ? ? ? = = l l(peak) i(dc) i i i 2 d = + ( ) l l(rms) i(dc) 2 2 i i i 12 d ? ? = + ? ? i l ? o s v min dmax i l d = , d = 50% ( ) ( ) ( ) ( ) o d o s m _ dc ind v v 1 l min i k 4 ? + 3 , d 50%, v with d closest to 50% i ( ) ( ) i o s m _ dc ind v d l min i k ? 3 ( ) ( ) o o m _ dc i est v i i v min = h
18 tps55340-q1 slvsbv5a ? june 2014 ? revised july 2016 www.ti.com product folder links: tps55340-q1 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 8.2.1.2.5 selecting the output capacitor (c8 through c10) at least 4.7 f of ceramic type x5r or x7r capacitance is recommended at the output. this output capacitance was selected to meet the requirements for the output ripple (v rip ) and voltage change during a load transient. the loop is then compensated for the selected output capacitor. the output capacitance must be selected based on the most stringent of these criteria. the output-ripple voltage is related to the capacitance and equivalent series resistance (esr) of the output capacitor. assuming a capacitor with zero esr, use equation 20 to calculate the minimum capacitance required for a given ripple. using high esr capacitors causes additional ripple. use equation 21 to calculate the maximum esr for a specified ripple. esr ripple can be neglected for ceramic capacitors but must be considered if tantalum or electrolytic capacitors are used. use equation 22 to calculate the minimum ceramic output capacitance required to meet a load transient requirement. use equation 23 to calculate the rms current required by the output capacitor for support. (20) (21) (22) (23) using equation 20 for this design, the minimum output capacitance for the specified 120-mv output ripple is 8.8 f. for a maximum transient-voltage change ( v (tran) ) of 960 mv with a 400 ma load transient ( i (tran) ), and a 6 khz control loop bandwidth ( ? bw ) with equation 22 , the minimum output capacitance is calculated as 11.1 f. the most stringent criteria is the 11.1 f for the required load transient. equation 23 calculates a 1.58-a rms current in the output capacitor. the capacitor must also be properly rated for the desired output voltage. care must be taken when evaluating ceramic capacitors that derate under dc bias, aging, and ac signal conditions. for example, larger form factor capacitors (in 1206 size) have self-resonant frequencies in the range of converter switching frequency. self-resonance significantly decreases the effective capacitance. the dc bias also significantly reduces capacitance. ceramic capacitors can lose as much as 50% of the capacitance when operated at the rated voltage. therefore, leave a margin when selecting the capacitor voltage rating to ensure adequate capacitance at the required output voltage. for this example, three 4.7- f, 50-v 1210 x7r ceramic capacitors are used in parallel leading to a negligible esr. selecting 50-v capacitors instead of 35-v capacitors reduces the effects of dc bias and allows this example circuit to be rated for the maximum output voltage range of the tps55340-q1 device. 8.2.1.2.6 selecting the input capacitors (c2 and c7) at least 4.7- f of ceramic input capacitance is recommended. additional input capacitance may be required to meet ripple requirements, transient requirements, or both. high-quality ceramic-type x5r or x7r capacitors are recommended to minimize capacitance variations over temperature. the capacitor must also have an rms- current rating greater than the maximum rms-input current of the tps55340-q1 device as calculated with equation 24 . the input capacitor must also be rated greater than the maximum input voltage. use equation 25 to calculate the input voltage ripple. (24) (25) l ci(rms) i i 12 d = ( ) co(rms) o dmax i i 1 dmax = - ( ) ( ) tran o bw tran i c 2 ? v d 3 p d o rip ? s o l dmax i v c esr i ? ? - ? ? d o o s rip dmax i c ? v 3 ( ) i(rip) l ci s i i l v i r 4 ? c d = + d
19 tps55340-q1 www.ti.com slvsbv5a ? june 2014 ? revised july 2016 product folder links: tps55340-q1 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated in the design example, the input rms current is calculated to be 191 ma. the selected input capacitor is a 10- f, 35-v 1210 x7r with 3 m esr. although a capacitor with a lower voltage rating can be used, a 35-v rated capacitor was selected to limit the affects of dc bias and to allow the circuit to be rated for the entire input range of the tps55340-q1 device. the input ripple is calculated to be 30 mv. an additional 0.1- f, 50-v 0603 x5r is located close to the vin pin and the gnd pin for additional decoupling. 8.2.1.2.7 setting the output voltage (r1 and r2) to set the output voltage in either dcm or ccm, use equation 26 and equation 27 to calculate the values of r1 and r2. (26) (27) considering the leakage current through the resistor divider and noise decoupling into fb pin, an optimum value for r2 is around 10 k . the output voltage tolerance depends on the v (fb) accuracy and the tolerance of r1 and r2. in this example, with a 24 v output, r1 is calculated to 185.3 k using equation 27 . the nearest standard value of 187 k is used. 8.2.1.2.8 setting the soft-start time (c7) select the appropriate capacitor to set soft-start time and avoid overshoot. increasing the soft-start time reduces the overshoot during start-up. a 0.047 f ceramic capacitor is used in this example. 8.2.1.2.9 selecting the schottky diode (d1) the high switching frequency of the tps55340-q1 device demands high-speed rectification for optimum efficiency. ensure that the average current rating and peak current rating of the diode exceed the average output current and peak inductor current. in addition, the reverse breakdown voltage of the diode must exceed the regulated output voltage. the diode must also be rated for the power dissipated which is calculated using equation 28 . p d = v (d) i o (28) in this conservative design example, the selected diode is rated for the maximum output current of 2.13 a. during normal operation with 800-ma output current and assuming a schottky diode drop of 0.5 v, the diode must be capable of dissipating 400 mw. the recommended minimum ratings for this design are a 40-v, 3-a diode. however to improve the flexibility of this design, a diodes inc b540-13-f in an smc package with voltage and current ratings of 40 v and 5 a was selected for this desigh. 8.2.1.2.10 compensating the control loop (r3, c4, and c5) the tps55340-q1 device requires external compensation which allows the loop response to be optimized for each application. the comp pin is the output of the internal error amplifier. an external resistor (r3) and ceramic capacitor (c4) are connected to the comp pin to provide a pole and a zero as shown in the application circuit (see figure 17 ). this pole and zero, along with the inherent pole and zero of a boost converter, determine the closed loop frequency response which is important for converter stability and transient response. loop compensation must be designed for the minimum operating voltage. the following equations summarize the loop equations for the tps55340-q1 device configured as a ccm boost converter. the equations include the power stage output pole ( ? o ) and the right-half-plane zero ( ? (rhpz) ) of a boost converter calculated using equation 29 and equation 30 respectively. when calculating ? o , including the derating of ceramic output capacitors is important. in the example with an estimated 10.2- f capacitance, these frequencies are calculated to be 980 khz and 22.1 khz respectively. use equation 29 to calculate the dc gain (a) of the power stage which is 39.9 db in this design. use equation 32 and equation 33 to calculate the compensation pole ( ? (p) ) and zero ( ? (z) ) generated by r3, c4, and the internal transconductance amplifier (respectively). o v r1 r2 1 1.229 v ? ? = - ? ? o r1 v 1.229 v 1 r2 ? ? = + ? ?
20 tps55340-q1 slvsbv5a ? june 2014 ? revised july 2016 www.ti.com product folder links: tps55340-q1 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated most ccm boost converters have a stable control loop if ? (z) is set slightly above ? (p) through proper sizing of r3 and c4. to start, select a value of 0.1 f for c4 and a value of 2 k for r3. increasing r3 or reducing c4 increases the closed loop bandwidth and therefore improves the transient response. adjusting r3 and c4 in opposite directions increases the phase and gain margin of the loop, which improves loop stability. ti recommends to limit the bandwidth of the loop to the lower of either 1/5 of the switching frequency ( ? s ) or 1/3 the rhpz frequency ( ? (rhpz) ) which is calculated using equation 30 . use the spreadsheet tool located as an aid in compensation design. see the tps55340-q1 product folder at www.ti.com . where ? c o is the equivalent output capacitor (c o = c8 + c9 + c10) ? r o is the equivalent load resistance (v o / i o ) (29) (30) where ? g ea is the error amplifier transconductance located in the electrical characteristics table ? r (sense) (15 m , typical) is the sense resistor in the current control loop (31) (32) (33) where ? ? co(1) is possible bandwidth (34) where ? ? co(2) is possible bandwidth (35) an additional capacitor from the comp pin to the gnd pin (c5) can be used to place a high frequency pole in the control loop. using this additional capacitor is not always required when using ceramic output capacitors. if a non-ceramic output capacitor is used, an additional zero ( ? (zesr) ) is located in the control loop. use equation 37 to calculate ? (zesr) . use equation 38 and equation 36 to calculate the value of c5 and the pole created by c5 (respectively). finally if additional phase margin is required, add an additional zero (f (zff) ) by placing a capacitor (c (ff) ) in parallel with the top feedback resistor (r1). ti recommends to place the zero at the target cross-over frequency or higher. the feed forward capacitor also adds a pole at a higher frequency. use equation 39 to calculate the recommended value of c (ff) . (36) (37) where ? r (esr) is the esr of the output capacitor (38) ( ) s co 1 ? ? 5 = ( ) z 1 ? 2 r3 c4 = p ( ) p 1 ? 2 10 m c4 = p w ( ) ( ) i o m ea o o sense v 1.229 1 a g 10 m r v v r 2 = w ( ) o i rhpz o 2 r v ? 2 l v ? ? ? ? p ? o o o 2 ? 2 r c ? p ( ) o esr r c c5 r3 = ( ) ( ) zesr o esr 1 ? 2 r c ? p ( ) p2 1 ? 2 r3 c5 = p ( ) ( ) rhpz co 2 ? ? 3 =
21 tps55340-q1 www.ti.com slvsbv5a ? june 2014 ? revised july 2016 product folder links: tps55340-q1 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated (39) if a network measurement tool is available, the most accurate compensation design can be achieved following this procedure. the power stage frequency response is first measured using a network analyzer at the minimum 5-v input and maximum 800-ma load. figure 18 shows this measurement. in this design only one pole and one zero are used and therefore the maximum phase increase from the compensation is 180 degrees. for a 60 degree phase margin, the power stage phase must be ? 120 degrees at the lowest point. based on the target 6-khz bandwidth, the measured power stage gain, k (ps) ( ? bw ), is 24.84 db and the phase is ? 110.3 degrees. figure 18. power stage gain and phase of the boost converter the value of r3 is then selected to set the compensation gain as the reciprocal of the power stage gain at the target bandwidth using equation 40 . the value of c4 is then selected to place a zero at 1/10 the target bandwidth using equation 41 . in this case r3 is calculated to be 2.56 k , the nearest standard value 2.55 k is used. the value of c4 is calculated to be 0.104 f and the nearest standard value of 0.100 f is used. a 100-pf capacitor is selected for c5 to add a high frequency pole at a frequency 100 times the target bandwidth, however adding 100 pf for c5 is not necessary because this design uses all ceramic capacitors. (40) (41) bw 1 c4 ? 2 r3 10 = p ( ) ( ) ( ) ( ) k ? bw ps 20 m ea 1 r3 r2 g 10 r1 r2 = ? ? ? ? + ? ? 180.0 150.0 120.0 90.0 60.0 30.0 0.0 60 40 20 0 20 40 60 100 1000 10000 100000 phase () gain (db) frequency (hz) gain phase c015 ( ) ( ) ff ref zff o 1 c v 2 r1 ? v = p
22 tps55340-q1 slvsbv5a ? june 2014 ? revised july 2016 www.ti.com product folder links: tps55340-q1 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 8.2.1.3 application curves the following application curves are characteristics of the boost converter. figure 19. efficiency versus output current v o (ac-coupled) = 500 mv/div i o = 200 ma/div figure 20. load transient response i l = 1 a/div v o (ac-coupled) = 100 mv/div v (sw) = 20 v/div figure 21. ccm pwm operation i l = 1 a/div v o (ac-coupled) = 10 mv/div v (sw) = 20 v/div figure 22. dcm pwm operation i l = 200 ma/div v o (ac-coupled) = 20 mv/div v (sw) = 20 v/div figure 23. pulse skipping v i = 1 v/div v (en) = 2 v/dvi v (sw) = 10 v/div v o = 10 v/div figure 24. startup v i en v o sw time 500 s/div v o sw i l time 1 ms/div v o i l sw time 1 s/div 50 55 60 65 70 75 80 85 90 95 100 0.0 0.4 0.8 1.2 1.6 2.0 efficiency (%) output current (a) vi = 5 v vi = 12 v c016 v i = 5 v v i = 12 v i o time 1 ms/div v o v o i l sw time 50 s/div
23 tps55340-q1 www.ti.com slvsbv5a ? june 2014 ? revised july 2016 product folder links: tps55340-q1 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated i o = 800 ma figure 25. closed loop gain and phase of the boost converter 8.2.2 tps55340-q1 sepic converter figure 26. sepic-converter application schematic 1 1 off 1 1 en on gnd not populated vout sync gnd gnd vin vin gnd gnd vout 12v, 1a 6-18v 1 12 3 jp1 12 j1 c4 0.1uf tp4 tp3 r4 95.3k tp2 1 2 j7 12 j5 1 2 j3 12 j6 r3 2.37k c5 1 2 j4 1 2 j2 c3 0.047uf c7 0.1uf r2 10k r5 49.9 c1 r6 0 c8 22uf r1 86.6k 1 sw 2 vin 3 en 4 ss 5 sync 6 agnd 7 comp 8 fb 9 freq 10 nc 11 pgnd 12 pgnd 13 pgnd 14 nc 15 sw 16 sw 17 pwpd u1 tps55340-q1 c9 22uf c10 22uf c11 c2 10uf l1 12uh c6 2.2uf tp1 d1 tp5 sync vin sync vin copyright ? 2016, texas instruments incorporated frequency (hz) gain (db) phase ( ) 100 1000 10000 100000 -60 -180 -40 -120 -20 -60 0 0 20 60 40 120 60 180 d001 5-v gain 5-v phase 15-v gain 15-v phase
24 tps55340-q1 slvsbv5a ? june 2014 ? revised july 2016 www.ti.com product folder links: tps55340-q1 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 8.2.2.1 design requirements the parameters listed in table 2 are used for a sepic converter design. these calculations are performed only for ccm operation. the use of a coupled inductor is assumed. table 2. key parameters of sepic converter example design parameter example value output voltage 12 v input voltage 6 v to 18 v, 12 v nominal maximum output current 1 a transient response 50% load step ( v o = 4%) 480 mv output voltage ripple (0.5% of v o ) 60 mv 8.2.2.2 detailed design procedure 8.2.2.2.1 selecting the switching frequency (r4) a 500-khz switching frequency ( ? s ) was selected for this design. use equation 1 and the nearest standard value 95.3 k to calculate the value of r4. 8.2.2.2.2 duty cycle use equation 42 to calculate the duty cycle of a sepic converter. selecting the 6-v minimum input the duty cycle is calculated as 68%. selecting the 18-v maximum input voltage the duty cycle is calculated as 41%. (42) 8.2.2.2.3 selecting the inductor (l1) with an estimated 85% efficiency, the input current is calculated to be 2.35 a using equation 11 . the minimum inductance is calculated to be 10.5 h using equation 43 with a k (ind) value of 0.3 and a maximum input value of 18-v. the nearest standard value of 12 h is used. this equation assumes that a coupled inductor is used. (43) the inductor ripple current is recalculated to be 615 ma using equation 44 . the peak current is calculated to be 3.69 a. for the saturation rating of the selected inductor, use the typical current-limit. the rms current for la is approximately the average input current 2.35 a. the rms current for lb is approximately the output current of 1 a. for this design a coilcraft msd1260-123 was used with 6.86-a saturation, 74-m dcr, and 3.12-a rms current rating for one winding. (44) (45) 8.2.2.2.4 calculating the maximum output current the maximum output current is calculated to be 1.47 a using equation 46 with the minimum input voltage of 6 v, selected inductance of 12 h, 5.25-a minimum current-limit, and estimated 85% efficiency. (46) ( ) ( ) o d o i d v v d v v v + = + + ( ) ( ) ( ) ( ) ( ) ( ) ( ) l i(dc) lim lim ind o o o i i est est i i i i k i max v v 1 1 v min v min - d - = = ? ? ? ? ? ? + + ? h ? h ? ? l l l(peak) l(a _ peak) l(b _ peak) i(dc) o i i i i i i i 2 2 d d ? ? ? ? = + = + + + ? ? ? ? i l s v max dmin i 2 ? l d = ( ) i s i(dc) ind v max dmin l 2 ? i k 3
25 tps55340-q1 www.ti.com slvsbv5a ? june 2014 ? revised july 2016 product folder links: tps55340-q1 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 8.2.2.2.5 selecting the output capacitor (c8 through c10) to meet the 60-mv ripple specification, the minimum output capacitance is calculated to be 22.5 f with equation 47 . this design uses ceramic output capacitors and the effects of esr are ignored. to meet the transient response of 500 ma with less than 480-mv voltage change and a 7-khz control loop bandwidth, the minimum output capacitance is calculated to be 23.7 f using equation 48 . the rms current is calculated to be 1.44 a using equation 24 . the output capacitors used in this design is three 22- f, 25-v x7r 1210 ceramic capacitors. with voltage derating, the effective total output capacitance is estimated to be 30.4 f. (47) (48) 8.2.2.2.6 selecting the series capacitor (c6) the series capacitor is chosen to limit the ripple current to 5% of the maximum input voltage. using equation 49 the minimum capacitance is 1.5 f. using equation 50 the rms current is calculated to be 1.63 a. a 2.2- f ceramic capacitor in a 1206 package was selected for this design. (49) (50) 8.2.2.2.7 selecting the input capacitor (c2 and c7) based on the minimum 4.7- f ceramic recommended for the tps55340-q1 device, a 10- f x7r input capacitor was used with an additional 0.1 f placed close to the vin pin and the gnd pin. with an estimated 6- f capacitance after voltage derating, the input ripple voltage is calculated to be 39.9 mv using equation 51 . the rms current of the input capacitance is calculated to be 0.177 a using equation 52 . (51) (52) 8.2.2.2.8 selecting the schottky diode (d1) the selected diode must have a minimum breakdown voltage (v (br) ). use equation 53 to calculate v (br) which is 30.5 v in this design. the average current rating is recommended to be greater than the maximum output current. with the maximum 18-v input, average current is calculated to be 2.6 a using equation 19 . the package must also be capable of handling the power dissipation. with an estimated 0.5 v forward voltage, power dissipation is calculated with equation 28 to be 500 mw. diodes inc b340b was chosen for this design with a 40- v, 3-a rating in a smb package. v (br) = v o + v i max + v f (53) 8.2.2.2.9 setting the output voltage (r1 and r2) with r2 fixed at 10 k , use equation 27 to calculate the nearest standard value of 86.6 k for r1. 8.2.2.2.10 setting the soft-start time (c3) the recommended 0.047- f soft-start capacitor is used for c3. 8.2.2.2.11 mosfet rating considerations in this design, with the maximum input voltage of 18 v and output voltage of 12 v, the fet receives approximately 30 v across drain and source. a 10% tolerance for the mosfet v ds rating is recommended to account for any ringing. the 40-v rating of the tps55340-q1 power mosfet comfortably satisfies this requirement. l (ci _ rms) i i 12 d = l i(rip) s i i v 4 ? c d = (cp _ rms) i(dc) (1 dmax) i i dmax - = ( ) o p i s i dmax c 0.05 v max ? 3 ( ) ( ) tran o bw tran i c 2 ? v d 3 p d o o s rip dmax i c ? v 3
26 tps55340-q1 slvsbv5a ? june 2014 ? revised july 2016 www.ti.com product folder links: tps55340-q1 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 8.2.2.2.12 compensating the control loop (r3 and c4) this design was compensated by measuring the frequency response of the power stage at the lowest input voltage of 6 v and choosing the components for the desired bandwidth. the lowest right-half plane zero ( ? (rhpz) ) is calculated with equation 54 to be 36.7 khz. when using the recommendation of limiting the bandwidth to 1/3 of ? (rhpz) or less, the recommended maximum bandwidth is 12.2 khz. (54) this design also uses only one pole and one zero. to achieve approximately 60 degrees of phase margin, the power stage phase must be no lower than approximately ? 120 degrees at the desired bandwidth. to ensure a stable design, r3 was initially set to 1 k and c4 was set to 1 f. figure 27 shows the measurement of the power stage. at 7 khz the power stage has a gain of 19.52 db and phase of ? 118.1 degrees. figure 27. sepic power stage gain and phase because no changes occur in the transconductance amplifier, the equations used to calculate the external compensation components in a boost design can be used in the sepic design. using the maximum g m(ea) from the electrical specification of 440 mho, equation 40 calculates the nearest standard value of r3 to be 2.37 k . using equation 41 , c4 is calculated to the nearest standard value of 0.1 f. 180 120 60 0 60 120 180 60 40 20 0 20 40 60 100 1000 10000 100000 phase () gain (db) frequency (hz) 6-v input gain 6-v input phase c018 ( ) ( ) o o rhpz 2 v i ? d 2 l 1 d = ? ? p ? ? - ?
27 tps55340-q1 www.ti.com slvsbv5a ? june 2014 ? revised july 2016 product folder links: tps55340-q1 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 8.2.2.3 application curves the following curves are characteristics of the sepic converter. figure 28. efficiency versus output current i o = 500 ma/div v o (ac-coupled) = 200 mv/div figure 29. load transient response v (sw) = 10 v/div i l(b) = 1 a/div i l(a) = 1 a/div v o (ac-coupled) = 50 mv/div figure 30. ccm pwm operation v i = 2 v/div v (en) = 2 v/div v (sw) = 20 v/div v o = 5 v/dvi figure 31. output voltage soft-start figure 32. closed loop gain and phase of the sepic converter v o i l(a) i l(b) sw time 2 s/div v o v i en sw time 1 ms/div 50 55 60 65 70 75 80 85 90 95 100 0.0 0.2 0.4 0.6 0.8 1.0 1.2 efficiency (%) output current (a) vi = 6 v vi = 12 v vi = 18 v c019 v i = 6 v v i = 12 v v i = 18 v v o i o time 500 s/div frequency (hz) gain (db) phase () 100 1000 10000 100000 -60 -180 -40 -120 -20 -60 0 0 20 60 40 120 60 180 d004 6-v gain 6-v phase 18-v gain 18-v phase
28 tps55340-q1 slvsbv5a ? june 2014 ? revised july 2016 www.ti.com product folder links: tps55340-q1 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 9 power supply recommendations the device is designed to operate from an input voltage supply range between 2.9 v and 32 v. this input supply must be well regulated. if the input supply is located more than a few inches from the tps55340-q1 converter additional bulk capacitance may be required in addition to the ceramic bypass capacitors. an electrolytic capacitor with a value of 100 f is a typical choice. 10 layout 10.1 layout guidelines as for all switching power supplies, especially those with high frequency and high switch current, printed circuit board (pcb) layout is an important design step. if the layout is not carefully designed, the regulator can suffer from instability as well as noise problems. the following guidelines are recommended for good pcb layout. ? to maximize efficiency, keep switch rise and fall times as short as possible. ? to prevent radiation of high frequency resonance problems, use proper layout of the high frequency switching path. ? minimize the length and area of all traces connected to the sw pin and always use a ground plane under the switching regulator to minimize inter-plane coupling. ? the high current path including the internal mosfet switch, schottky diode, and output capacitor, contains nanosecond rise times and fall times. keep these rise times and fall times as short as possible. ? place the input capacitor as close to the vin pin and the agnd pin as possible to reduce the ic supply ripple. 10.2 layout example figure 33. tps55340-q1 example board layout l o output filter capacitor v o v i power ground power ground v i bypass capacitor v i high-frequency bypass capacitor c (ss) c i feedback resistors frequency set resistor connect to v o on the inner or bottom layer connect to agnd on the inner or bottom layer output filter capacitor compensation network uvlo resistors bypass capacitor for tps55340-q1 . put close to pin 2 9 10 12 11 4 3 1 2 5 6 8 7 sw 16 15 13 14 powerpad sw nc pgnd sync agnd comp fb ss en vin sw freq nc pgnd pgnd
29 tps55340-q1 www.ti.com slvsbv5a ? june 2014 ? revised july 2016 product folder links: tps55340-q1 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 11 device and documentation support 11.1 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 11.2 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.3 trademarks powerpad, e2e are trademarks of texas instruments. webench is a registered trademark of texas instruments. all other trademarks are the property of their respective owners. 11.4 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.5 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 1-jul-2016 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples tps55340qrterq1 active wqfn rte 16 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 55340q TPS55340QRTETQ1 active wqfn rte 16 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 55340q (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release.
package option addendum www.ti.com 1-jul-2016 addendum-page 2 in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of tps55340-q1 : ? catalog: tps55340 ? enhanced product: tps55340-ep note: qualified version definitions: ? catalog - ti's standard catalog product ? enhanced product - supports defense, aerospace and medical applications
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant tps55340qrterq1 wqfn rte 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 q2 TPS55340QRTETQ1 wqfn rte 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 q2 package materials information www.ti.com 1-jul-2016 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) tps55340qrterq1 wqfn rte 16 3000 367.0 367.0 35.0 TPS55340QRTETQ1 wqfn rte 16 250 210.0 185.0 35.0 package materials information www.ti.com 1-jul-2016 pack materials-page 2

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